|
Tahir Ghani is an Intel Fellow and director of transistor technology and integration. He is currently leading the front-end process integration team responsible for transistor design and front-end processor integration for Intel’s 32nm logic technology node.
Since joining Intel is 1994 Ghani has held several different positions. As a Senior Device Engineer he was responsible for Intel’s 0.25um transistor device development and as a Senior Process Integration Engineer he managed development of industry leading transistor technology for Intel’s 180nm logic node. Ghani was also Integration Group Leader for 90nm logic node where he led the team responsible for developing Intel’s 90nm front end process technology exercising strained silicon transistors. Ghani and co-workers were the first to publish a novel epitaxial SiGe source drain transistor which introduced high levels of strain for significant PMOS mobility enhancement.
Ghani has received two Intel Achievement Awards. The first awarded in 1996 was for his role in developing leading-edge 0.25um CMOS transistor technology. He received the second in 2003 for developing uniaxially strained silicon transistor technology for Intel’s 90nm logic technology node. He has published 28 technical papers many of which were presented at leading technical conferences.
Ghani received his B.S. in electrical engineering at the University of Engineering and Technology in Lahore Pakistan in 1985 and his Ph.D. in electrical engineering at Stanford University in 1994. He is a member of IEEE. | 