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Specialist in high performance, high functionality, TTL and ECL digital circuit design with emphasis in FPGA's, CPLD's and ASIC's. Analog design experience includes A/D's, D/A's and video filtering. Direct design experience in Xilinx (3000 and 4000 series), Actel (ACT1,2,3), AMD Mach, Altera MAX (5000, 7000, 8000 series), Atmel, QuickLogic, and Cypress FPGA's. Gate array experience with LSI 100k/300k/400k technologies. ECL experience in both 100k and 100kh technologies. Programming in 'C' (including Windows), AWK and PERL. Synthesis expertise using VHDL/Verilog with Exemplar, Synplicity, and ViewLogic. Contract assignments include a variety of management consulting and seminar presentations. Present hardware designs include a PCI-based multiprocessing SHARC DSP engine for high performance audio applications, a 170 MHz ECL data acquisition controller and frame buffer, and several low cost gate arrays for satellite cable decoders (NTSC and PALM). Gate Array design and FPGA to gate array translation using Exemplar and ViewLogic. Founding member of PREP Benchmark User's group and PREP verification center.
HDL's: ABEL, CUPL, PALASM, VHDL, AHDL, Verilog
Schematic Capture: FutureNet, ViewLogic, Orcad, CAD/CAM
Synthesis: Exemplar CORE , ViewLogic ViewSynthesis, Synplicity
Programming languages: Microsoft 'C', Windows, AWK, PERL
Gate Arrays: LSI 100k/300k/400k, CMDE 2.0
FPGA's: Xilinx (3000, 4000 series), Actel (ACT1, ACT2, ACT3), AMD MACH, Altera MAX (5000, 7000, 8000 series), Atmel, QuickLogic, Cypress, Crosspoint. | 