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Ken Tseng, CTO & Founder Prior to founding Altos, Ken was a Cadence Architect responsible for signal integrity analysis tools PacifIC and CeltIC. At CadMOS, Ken was an R&D Director and the original author of CeltIC. Prior to that, he held R&D positions at Synopsys, Logic Modeling, Zycad and AMD. Ken holds multiple patents in timing, signal integrity and microprocessor design. He is an expert in circuit analysis, logic abstraction and signal integrity. He holds an MSEE/BSEE from UT Austin and has 20 years experience in EDA. | 