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Dr.Sanguinetti is presently the CTO of Forte Design Systems. He has been active in computer architecture, performance analysis, and design verification for 20 years. After working for DEC, Amdahl, ELXSI, Ardent, and NeXT computer manufacturers, he founded Chronologic Simulation in 1991 and was President until 1995. He was the principal architect of VCS, the Verilog Compiled Simulator, and was a major contributor to the resurgence in the use of Verilog in the design community. Dr. Sanguinetti served on the Open Verilog International Board of Directors from 1992 to 1995 and was a major contributor to the working group, which drafted the specification for the IEEE 1364 Verilog standard. He was a co-founder of CynApps. He has 15 publications and one patent.
Dr. Sanguinetti's Ph.D. is in Computer and Communication Sciences from the University of Michigan. | 