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George E. Sery is an Intel Fellow and Director of Device Technology Optimization in Intel's California Technology and Manufacturing Group. Sery is currently responsible for directing process development for Intel's 65nm FLASH memory technology.
Sery received his bachelor's and master's degrees in electrical engineering from the University of Minnesota in 1976 and 1978 respectively. He joined Intel in 1978 as part of the SRAM Technology Development group.
Sery has been involved with development of NMOS and CMOS technologies for logic, SRAM, and Flash memory applications. For each technology, he has led the device physics team responsible for device development and process characterization.
Sery has received three Intel Achievement Awards for Flash memory and logic development improvements. He has co-authored numerous publications related to logic and Flash memory development, holds patents in Flash and logic technology and is a member of the IEEE. | 